Kemal Derya

WPI, AK212, 100 Institute Rd

Worcester, MA 01609

I’m currently a Ph.D. candidate at Worcester Polytechnic Institute in Massachusetts, USA, advised by Berk Sunar. My research interests include microarchitectural security, post-quantum cryptography, and AI safety.

My current work focuses on hardware-based attacks and defenses, particularly side-channel and fault injection techniques that target cryptographic implementations. In parallel, I am investigating the intersection of AI and cryptography, including how machine learning systems can be compromised through cryptographic approach.

Prior to starting my Ph.D., I received both my B.S. and M.S. degrees in Electronics Engineering from Sabancı University in Istanbul, Turkey. During my graduate studies, I worked on FPGA implementation of post-quantum cryptography schemes.

news

Jul 03, 2025	LeapFrog presented at EuroS&P 2025.
Apr 22, 2025	FAULT+PROBE accepted at AsiaCCS 2025
Jan 13, 2025	Started at Analog Devices Inc. as a System Engineer Intern.

selected publications

Non-Halting Queries: Exploiting Fixed Points in LLMs

Ghaith Hammouri, Kemal Derya, and Berk Sunar

In 2025 IEEE Conference on Secure and Trustworthy Machine Learning (SaTML), 2025

DOI
Fault+ probe: A generic rowhammer-based bit recovery attack

Kemal Derya, M Caner Tol, and Berk Sunar

arXiv preprint arXiv:2406.06943, 2024
CoHA-NTT: A Configurable Hardware Accelerator for NTT-based Polynomial Multiplication

Kemal Derya, Ahmet Can Mert, Erdinç Öztürk, and 1 more author

Microprocessors and Microsystems, 2022

Abs DOI

In this paper, we introduce a configurable hardware architecture that can be used to generate unified and parametric NTT-based polynomial multipliers that support a wide range of parameters of lattice-based cryptographic schemes proposed for post-quantum cryptography. Both NTT and inverse NTT operations can be performed using the unified butterfly unit of our architecture, which constitutes the core building block in NTT operations. The multitude of this unit plays an essential role in achieving the performance goals of a specific application area or platform. To this end, the architecture takes the size of butterfly units as input and generates an efficient NTT-based polynomial multiplier hardware to achieve the desired throughput and area requirements. More specifically, the proposed hardware architecture provides run-time configurability for the scheme parameters and compile-time configurability for throughput and area requirements. This work presents the first architecture with both run-time and compile-time configurability for NTT-based polynomial multiplication operations to the best of our knowledge. The implementation results indicate that the advanced configurability has a negligible impact on the time and area of the proposed architecture and that its performance is on par with the state-of-the-art implementations in the literature, if not better. The proposed architecture comprises various sub-blocks such as modular multiplier and butterfly units, each of which can be of interest on its own for accelerating lattice-based cryptography. Thus, we provide the design rationale of each sub-block and compare it with those in the literature, including our earlier works in terms of configurability and performance.